Gabe/advent_of_code_2022
1
0
Fork 0
Code Issues Pull requests Projects Releases Wiki Activity

day10 part 1.

Browse source
This commit is contained in:
Gabe Venberg 2023-11-24 19:03:39 -06:00 • committed by Gabe Venberg
parent 3b18b90bda
commit 711dbb63d2
14 changed files with 1005 additions and 18 deletions
Download patch file Download diff file Expand all files Collapse all files

10
days/day10/Cargo.toml Normal file
View file

@ -0,0 +1,10 @@
[package]
name = "day10"
authors.workspace = true
description.workspace = true
version.workspace = true
edition.workspace = true
[dependencies]
aoc_libs.workspace = true
nom.workspace = true

139
days/day10/src/input.txt Normal file
View file

@ -0,0 +1,139 @@
noop
addx 12
addx -5
addx -1
noop
addx 4
noop
addx 1
addx 4
noop
addx 13
addx -8
noop
addx -19
addx 24
addx 1
noop
addx 4
noop
addx 1
addx 5
addx -1
addx -37
addx 16
addx -13
addx 18
addx -11
addx 2
addx 23
noop
addx -18
addx 9
addx -8
addx 2
addx 5
addx 2
addx -21
addx 26
noop
addx -15
addx 20
noop
addx 3
noop
addx -38
addx 3
noop
addx 26
addx -4
addx -19
addx 3
addx 1
addx 5
addx 3
noop
addx 2
addx 3
noop
addx 2
noop
noop
noop
noop
addx 5
noop
noop
noop
addx 3
noop
addx -30
addx -4
addx 1
addx 18
addx -8
addx -4
addx 2
noop
addx 7
noop
noop
noop
noop
addx 5
noop
noop
addx 5
addx -2
addx -20
addx 27
addx -20
addx 25
addx -2
addx -35
noop
noop
addx 4
addx 3
addx -2
addx 5
addx 2
addx -11
addx 1
addx 13
addx 2
addx 5
addx 6
addx -1
addx -2
noop
addx 7
addx -2
addx 6
addx 1
addx -21
addx 22
addx -38
addx 5
addx 3
addx -1
noop
noop
addx 5
addx 1
addx 4
addx 3
addx -2
addx 2
noop
addx 7
addx -1
addx 2
addx 4
addx -10
addx -19
addx 35
addx -1
noop
noop
noop

256
days/day10/src/machine.rs Normal file
View file

@ -0,0 +1,256 @@
use std::{collections::VecDeque, fmt};
use crate::parse::*;
pub struct Machine {
instructions: VecDeque<Instruction>,
current_instruction: Option<(Instruction, usize)>,
cycle: usize,
x: i32,
}
impl Machine {
pub fn load_program(instructions: VecDeque<Instruction>) -> Self {
let mut res = Machine {
instructions,
current_instruction: None,
cycle: 0,
x: 1,
};
res.fetch_next_instruction();
res
}
pub fn step(&mut self) -> bool {
if self.current_instruction.is_none() {
return false;
}
let (instruction, cycles_left) = self.current_instruction.as_mut().unwrap();
*cycles_left -= 1;
if *cycles_left == 0 {
if let Instruction::Addx(i) = instruction {
self.x += *i
}
self.fetch_next_instruction();
};
self.cycle += 1;
true
}
fn fetch_next_instruction(&mut self) {
self.current_instruction = self.instructions.pop_front().map(|i| (i, i.cycles()));
}
//returns the signal strength during the middle of the 20th cycle.
pub fn step20(&mut self) -> i32 {
for _ in 0..19 {
if !self.step() {
break;
}
}
let ret = self.x*(self.cycle as i32 +1);
self.step();
ret
}
pub fn signal_strength(&self) -> i32 {
self.x * (self.cycle as i32)
}
}
impl fmt::Debug for Machine {
fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
write!(
f,
"cycle={} x={} current instruction: {:?} ({} instructions left)",
self.cycle,
self.x,
self.current_instruction,
self.instructions.len()
)
}
}
#[cfg(test)]
mod tests {
use super::*;
#[test]
fn test_machine() {
let input = vec![
Instruction::Addx(15),
Instruction::Addx(-11),
Instruction::Addx(6),
Instruction::Addx(-3),
Instruction::Addx(5),
Instruction::Addx(-1),
Instruction::Addx(-8),
Instruction::Addx(13),
Instruction::Addx(4),
Instruction::NoOp,
Instruction::Addx(-1),
Instruction::Addx(5),
Instruction::Addx(-1),
Instruction::Addx(5),
Instruction::Addx(-1),
Instruction::Addx(5),
Instruction::Addx(-1),
Instruction::Addx(5),
Instruction::Addx(-1),
Instruction::Addx(-35),
Instruction::Addx(1),
Instruction::Addx(24),
Instruction::Addx(-19),
Instruction::Addx(1),
Instruction::Addx(16),
Instruction::Addx(-11),
Instruction::NoOp,
Instruction::NoOp,
Instruction::Addx(21),
Instruction::Addx(-15),
Instruction::NoOp,
Instruction::NoOp,
Instruction::Addx(-3),
Instruction::Addx(9),
Instruction::Addx(1),
Instruction::Addx(-3),
Instruction::Addx(8),
Instruction::Addx(1),
Instruction::Addx(5),
Instruction::NoOp,
Instruction::NoOp,
Instruction::NoOp,
Instruction::NoOp,
Instruction::NoOp,
Instruction::Addx(-36),
Instruction::NoOp,
Instruction::Addx(1),
Instruction::Addx(7),
Instruction::NoOp,
Instruction::NoOp,
Instruction::NoOp,
Instruction::Addx(2),
Instruction::Addx(6),
Instruction::NoOp,
Instruction::NoOp,
Instruction::NoOp,
Instruction::NoOp,
Instruction::NoOp,
Instruction::Addx(1),
Instruction::NoOp,
Instruction::NoOp,
Instruction::Addx(7),
Instruction::Addx(1),
Instruction::NoOp,
Instruction::Addx(-13),
Instruction::Addx(13),
Instruction::Addx(7),
Instruction::NoOp,
Instruction::Addx(1),
Instruction::Addx(-33),
Instruction::NoOp,
Instruction::NoOp,
Instruction::NoOp,
Instruction::Addx(2),
Instruction::NoOp,
Instruction::NoOp,
Instruction::NoOp,
Instruction::Addx(8),
Instruction::NoOp,
Instruction::Addx(-1),
Instruction::Addx(2),
Instruction::Addx(1),
Instruction::NoOp,
Instruction::Addx(17),
Instruction::Addx(-9),
Instruction::Addx(1),
Instruction::Addx(1),
Instruction::Addx(-3),
Instruction::Addx(11),
Instruction::NoOp,
Instruction::NoOp,
Instruction::Addx(1),
Instruction::NoOp,
Instruction::Addx(1),
Instruction::NoOp,
Instruction::NoOp,
Instruction::Addx(-13),
Instruction::Addx(-19),
Instruction::Addx(1),
Instruction::Addx(3),
Instruction::Addx(26),
Instruction::Addx(-30),
Instruction::Addx(12),
Instruction::Addx(-1),
Instruction::Addx(3),
Instruction::Addx(1),
Instruction::NoOp,
Instruction::NoOp,
Instruction::NoOp,
Instruction::Addx(-9),
Instruction::Addx(18),
Instruction::Addx(1),
Instruction::Addx(2),
Instruction::NoOp,
Instruction::NoOp,
Instruction::Addx(9),
Instruction::NoOp,
Instruction::NoOp,
Instruction::NoOp,
Instruction::Addx(-1),
Instruction::Addx(2),
Instruction::Addx(-37),
Instruction::Addx(1),
Instruction::Addx(3),
Instruction::NoOp,
Instruction::Addx(15),
Instruction::Addx(-21),
Instruction::Addx(22),
Instruction::Addx(-6),
Instruction::Addx(1),
Instruction::NoOp,
Instruction::Addx(2),
Instruction::Addx(1),
Instruction::NoOp,
Instruction::Addx(-10),
Instruction::NoOp,
Instruction::NoOp,
Instruction::Addx(20),
Instruction::Addx(1),
Instruction::Addx(2),
Instruction::Addx(2),
Instruction::Addx(-6),
Instruction::Addx(-11),
Instruction::NoOp,
Instruction::NoOp,
Instruction::NoOp,
];
let mut machine = Machine::load_program(input.into());
//20th
assert_eq!(machine.step20(), 420);
machine.step20();
//60th
assert_eq!(machine.step20(), 1140);
machine.step20();
//100th
assert_eq!(machine.step20(), 1800);
machine.step20();
//140th
assert_eq!(machine.step20(), 2940);
machine.step20();
//180th
assert_eq!(machine.step20(), 2880);
machine.step20();
//220th
assert_eq!(machine.step20(), 3960);
}
}

15
days/day10/src/main.rs Normal file
View file

@ -0,0 +1,15 @@
mod part1;
mod part2;
mod parse;
mod machine;
fn main() {
let input = include_str!("./input.txt");
let structured_input = parse::parse(input);
println!("Part One");
println!("Result: {}", part1::part1(structured_input));
println!("Part Two");
println!("Result: {}", part2::part2());
}

344
days/day10/src/parse.rs Normal file
View file

@ -0,0 +1,344 @@
use std::collections::VecDeque;
use nom::{
branch::alt,
bytes::complete::tag,
combinator::{all_consuming, map, value},
sequence::preceded,
Finish, IResult,
};
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Instruction {
NoOp,
Addx(i32),
}
impl Instruction {
fn parse(i: &str) -> IResult<&str, Self> {
let noop = tag("noop");
let addx = preceded(tag("addx "), nom::character::complete::i32);
alt((value(Self::NoOp, noop), map(addx, Self::Addx)))(i)
}
pub fn cycles(self) -> usize {
match self {
Self::NoOp => 1,
Self::Addx(_) => 2,
}
}
}
pub fn parse(input: &str) -> VecDeque<Instruction> {
input
.lines()
.map(|l| all_consuming(Instruction::parse)(l).finish().unwrap().1)
.collect()
}
#[cfg(test)]
mod tests {
use super::*;
#[test]
fn test_parse() {
let input = concat!(
"addx 15\n",
"addx -11\n",
"addx 6\n",
"addx -3\n",
"addx 5\n",
"addx -1\n",
"addx -8\n",
"addx 13\n",
"addx 4\n",
"noop\n",
"addx -1\n",
"addx 5\n",
"addx -1\n",
"addx 5\n",
"addx -1\n",
"addx 5\n",
"addx -1\n",
"addx 5\n",
"addx -1\n",
"addx -35\n",
"addx 1\n",
"addx 24\n",
"addx -19\n",
"addx 1\n",
"addx 16\n",
"addx -11\n",
"noop\n",
"noop\n",
"addx 21\n",
"addx -15\n",
"noop\n",
"noop\n",
"addx -3\n",
"addx 9\n",
"addx 1\n",
"addx -3\n",
"addx 8\n",
"addx 1\n",
"addx 5\n",
"noop\n",
"noop\n",
"noop\n",
"noop\n",
"noop\n",
"addx -36\n",
"noop\n",
"addx 1\n",
"addx 7\n",
"noop\n",
"noop\n",
"noop\n",
"addx 2\n",
"addx 6\n",
"noop\n",
"noop\n",
"noop\n",
"noop\n",
"noop\n",
"addx 1\n",
"noop\n",
"noop\n",
"addx 7\n",
"addx 1\n",
"noop\n",
"addx -13\n",
"addx 13\n",
"addx 7\n",
"noop\n",
"addx 1\n",
"addx -33\n",
"noop\n",
"noop\n",
"noop\n",
"addx 2\n",
"noop\n",
"noop\n",
"noop\n",
"addx 8\n",
"noop\n",
"addx -1\n",
"addx 2\n",
"addx 1\n",
"noop\n",
"addx 17\n",
"addx -9\n",
"addx 1\n",
"addx 1\n",
"addx -3\n",
"addx 11\n",
"noop\n",
"noop\n",
"addx 1\n",
"noop\n",
"addx 1\n",
"noop\n",
"noop\n",
"addx -13\n",
"addx -19\n",
"addx 1\n",
"addx 3\n",
"addx 26\n",
"addx -30\n",
"addx 12\n",
"addx -1\n",
"addx 3\n",
"addx 1\n",
"noop\n",
"noop\n",
"noop\n",
"addx -9\n",
"addx 18\n",
"addx 1\n",
"addx 2\n",
"noop\n",
"noop\n",
"addx 9\n",
"noop\n",
"noop\n",
"noop\n",
"addx -1\n",
"addx 2\n",
"addx -37\n",
"addx 1\n",
"addx 3\n",
"noop\n",
"addx 15\n",
"addx -21\n",
"addx 22\n",
"addx -6\n",
"addx 1\n",
"noop\n",
"addx 2\n",
"addx 1\n",
"noop\n",
"addx -10\n",
"noop\n",
"noop\n",
"addx 20\n",
"addx 1\n",
"addx 2\n",
"addx 2\n",
"addx -6\n",
"addx -11\n",
"noop\n",
"noop\n",
"noop\n",
);
assert_eq!(
parse(input),
vec![
Instruction::Addx(15),
Instruction::Addx(-11),
Instruction::Addx(6),
Instruction::Addx(-3),
Instruction::Addx(5),
Instruction::Addx(-1),
Instruction::Addx(-8),
Instruction::Addx(13),
Instruction::Addx(4),
Instruction::NoOp,
Instruction::Addx(-1),
Instruction::Addx(5),
Instruction::Addx(-1),
Instruction::Addx(5),
Instruction::Addx(-1),
Instruction::Addx(5),
Instruction::Addx(-1),
Instruction::Addx(5),
Instruction::Addx(-1),
Instruction::Addx(-35),
Instruction::Addx(1),
Instruction::Addx(24),
Instruction::Addx(-19),
Instruction::Addx(1),
Instruction::Addx(16),
Instruction::Addx(-11),
Instruction::NoOp,
Instruction::NoOp,
Instruction::Addx(21),
Instruction::Addx(-15),
Instruction::NoOp,
Instruction::NoOp,
Instruction::Addx(-3),
Instruction::Addx(9),
Instruction::Addx(1),
Instruction::Addx(-3),
Instruction::Addx(8),
Instruction::Addx(1),
Instruction::Addx(5),
Instruction::NoOp,
Instruction::NoOp,
Instruction::NoOp,
Instruction::NoOp,
Instruction::NoOp,
Instruction::Addx(-36),
Instruction::NoOp,
Instruction::Addx(1),
Instruction::Addx(7),
Instruction::NoOp,
Instruction::NoOp,
Instruction::NoOp,
Instruction::Addx(2),
Instruction::Addx(6),
Instruction::NoOp,
Instruction::NoOp,
Instruction::NoOp,
Instruction::NoOp,
Instruction::NoOp,
Instruction::Addx(1),
Instruction::NoOp,
Instruction::NoOp,
Instruction::Addx(7),
Instruction::Addx(1),
Instruction::NoOp,
Instruction::Addx(-13),
Instruction::Addx(13),
Instruction::Addx(7),
Instruction::NoOp,
Instruction::Addx(1),
Instruction::Addx(-33),
Instruction::NoOp,
Instruction::NoOp,
Instruction::NoOp,
Instruction::Addx(2),
Instruction::NoOp,
Instruction::NoOp,
Instruction::NoOp,
Instruction::Addx(8),
Instruction::NoOp,
Instruction::Addx(-1),
Instruction::Addx(2),
Instruction::Addx(1),
Instruction::NoOp,
Instruction::Addx(17),
Instruction::Addx(-9),
Instruction::Addx(1),
Instruction::Addx(1),
Instruction::Addx(-3),
Instruction::Addx(11),
Instruction::NoOp,
Instruction::NoOp,
Instruction::Addx(1),
Instruction::NoOp,
Instruction::Addx(1),
Instruction::NoOp,
Instruction::NoOp,
Instruction::Addx(-13),
Instruction::Addx(-19),
Instruction::Addx(1),
Instruction::Addx(3),
Instruction::Addx(26),
Instruction::Addx(-30),
Instruction::Addx(12),
Instruction::Addx(-1),
Instruction::Addx(3),
Instruction::Addx(1),
Instruction::NoOp,
Instruction::NoOp,
Instruction::NoOp,
Instruction::Addx(-9),
Instruction::Addx(18),
Instruction::Addx(1),
Instruction::Addx(2),
Instruction::NoOp,
Instruction::NoOp,
Instruction::Addx(9),
Instruction::NoOp,
Instruction::NoOp,
Instruction::NoOp,
Instruction::Addx(-1),
Instruction::Addx(2),
Instruction::Addx(-37),
Instruction::Addx(1),
Instruction::Addx(3),
Instruction::NoOp,
Instruction::Addx(15),
Instruction::Addx(-21),
Instruction::Addx(22),
Instruction::Addx(-6),
Instruction::Addx(1),
Instruction::NoOp,
Instruction::Addx(2),
Instruction::Addx(1),
Instruction::NoOp,
Instruction::Addx(-10),
Instruction::NoOp,
Instruction::NoOp,
Instruction::Addx(20),
Instruction::Addx(1),
Instruction::Addx(2),
Instruction::Addx(2),
Instruction::Addx(-6),
Instruction::Addx(-11),
Instruction::NoOp,
Instruction::NoOp,
Instruction::NoOp
]
);
}
}

191
days/day10/src/part1.rs Normal file
View file

@ -0,0 +1,191 @@
use std::collections::VecDeque;
use crate::{parse::*, machine::Machine};
pub fn part1(input: VecDeque<Instruction>) -> i32 {
let mut machine = Machine::load_program(input.into());
let mut total = 0;
//20th
total+=machine.step20();
machine.step20();
//60th
total+=machine.step20();
machine.step20();
//100th
total+=machine.step20();
machine.step20();
//140th
total+=machine.step20();
machine.step20();
//180th
total+=machine.step20();
machine.step20();
//220th
total+=machine.step20();
total
}
#[cfg(test)]
mod tests {
use super::*;
#[test]
fn test_part1() {
let input = vec![
Instruction::Addx(15),
Instruction::Addx(-11),
Instruction::Addx(6),
Instruction::Addx(-3),
Instruction::Addx(5),
Instruction::Addx(-1),
Instruction::Addx(-8),
Instruction::Addx(13),
Instruction::Addx(4),
Instruction::NoOp,
Instruction::Addx(-1),
Instruction::Addx(5),
Instruction::Addx(-1),
Instruction::Addx(5),
Instruction::Addx(-1),
Instruction::Addx(5),
Instruction::Addx(-1),
Instruction::Addx(5),
Instruction::Addx(-1),
Instruction::Addx(-35),
Instruction::Addx(1),
Instruction::Addx(24),
Instruction::Addx(-19),
Instruction::Addx(1),
Instruction::Addx(16),
Instruction::Addx(-11),
Instruction::NoOp,
Instruction::NoOp,
Instruction::Addx(21),
Instruction::Addx(-15),
Instruction::NoOp,
Instruction::NoOp,
Instruction::Addx(-3),
Instruction::Addx(9),
Instruction::Addx(1),
Instruction::Addx(-3),
Instruction::Addx(8),
Instruction::Addx(1),
Instruction::Addx(5),
Instruction::NoOp,
Instruction::NoOp,
Instruction::NoOp,
Instruction::NoOp,
Instruction::NoOp,
Instruction::Addx(-36),
Instruction::NoOp,
Instruction::Addx(1),
Instruction::Addx(7),
Instruction::NoOp,
Instruction::NoOp,
Instruction::NoOp,
Instruction::Addx(2),
Instruction::Addx(6),
Instruction::NoOp,
Instruction::NoOp,
Instruction::NoOp,
Instruction::NoOp,
Instruction::NoOp,
Instruction::Addx(1),
Instruction::NoOp,
Instruction::NoOp,
Instruction::Addx(7),
Instruction::Addx(1),
Instruction::NoOp,
Instruction::Addx(-13),
Instruction::Addx(13),
Instruction::Addx(7),
Instruction::NoOp,
Instruction::Addx(1),
Instruction::Addx(-33),
Instruction::NoOp,
Instruction::NoOp,
Instruction::NoOp,
Instruction::Addx(2),
Instruction::NoOp,
Instruction::NoOp,
Instruction::NoOp,
Instruction::Addx(8),
Instruction::NoOp,
Instruction::Addx(-1),
Instruction::Addx(2),
Instruction::Addx(1),
Instruction::NoOp,
Instruction::Addx(17),
Instruction::Addx(-9),
Instruction::Addx(1),
Instruction::Addx(1),
Instruction::Addx(-3),
Instruction::Addx(11),
Instruction::NoOp,
Instruction::NoOp,
Instruction::Addx(1),
Instruction::NoOp,
Instruction::Addx(1),
Instruction::NoOp,
Instruction::NoOp,
Instruction::Addx(-13),
Instruction::Addx(-19),
Instruction::Addx(1),
Instruction::Addx(3),
Instruction::Addx(26),
Instruction::Addx(-30),
Instruction::Addx(12),
Instruction::Addx(-1),
Instruction::Addx(3),
Instruction::Addx(1),
Instruction::NoOp,
Instruction::NoOp,
Instruction::NoOp,
Instruction::Addx(-9),
Instruction::Addx(18),
Instruction::Addx(1),
Instruction::Addx(2),
Instruction::NoOp,
Instruction::NoOp,
Instruction::Addx(9),
Instruction::NoOp,
Instruction::NoOp,
Instruction::NoOp,
Instruction::Addx(-1),
Instruction::Addx(2),
Instruction::Addx(-37),
Instruction::Addx(1),
Instruction::Addx(3),
Instruction::NoOp,
Instruction::Addx(15),
Instruction::Addx(-21),
Instruction::Addx(22),
Instruction::Addx(-6),
Instruction::Addx(1),
Instruction::NoOp,
Instruction::Addx(2),
Instruction::Addx(1),
Instruction::NoOp,
Instruction::Addx(-10),
Instruction::NoOp,
Instruction::NoOp,
Instruction::Addx(20),
Instruction::Addx(1),
Instruction::Addx(2),
Instruction::Addx(2),
Instruction::Addx(-6),
Instruction::Addx(-11),
Instruction::NoOp,
Instruction::NoOp,
Instruction::NoOp,
];
assert_eq!(part1(input.into()), 13140)
}
}

15
days/day10/src/part2.rs Normal file
View file

@ -0,0 +1,15 @@
use crate::parse::*;
pub fn part2() -> usize {
unimplemented!()
}
#[cfg(test)]
mod tests {
use super::*;
#[test]
fn test_part2() {
assert_eq!(0, 0);
}
}