66 lines
1.9 KiB
Makefile
66 lines
1.9 KiB
Makefile
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CC := gcc
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CXX := g++
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OPTIMIZATION := -O3
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CFLAGS = ${OPTIMIZATION} -Werror -Wextra -Wall -Wpedantic
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# all: helloworld
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#
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# #automatically built from implicit rules.
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# helloworld: helloworld.c
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#
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# clean:
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# rm -f helloworld
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#
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TARGET_EXEC := combinations
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BUILD_DIR := ./build
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SRC_DIRS := ./src
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# Find all the C and C++ files we want to compile
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# Note the single quotes around the * expressions. The shell will incorrectly expand these otherwise, but we want to send the * directly to the find command.
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SRCS := $(shell find $(SRC_DIRS) -name '*.cpp' -or -name '*.c' -or -name '*.s')
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# Prepends BUILD_DIR and appends .o to every src file
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# As an example, ./your_dir/hello.cpp turns into ./build/./your_dir/hello.cpp.o
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OBJS := $(SRCS:%=$(BUILD_DIR)/%.o)
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# String substitution (suffix version without %).
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# As an example, ./build/hello.cpp.o turns into ./build/hello.cpp.d
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DEPS := $(OBJS:.o=.d)
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# Every folder in ./src will need to be passed to GCC so that it can find header files
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INC_DIRS := $(shell find $(SRC_DIRS) -type d)
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# Add a prefix to INC_DIRS. So moduleA would become -ImoduleA. GCC understands this -I flag
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INC_FLAGS := $(addprefix -I,$(INC_DIRS))
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# The -MMD and -MP flags together generate Makefiles for us!
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# These files will have .d instead of .o as the output.
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DEPFLAGS := $(INC_FLAGS) -MMD -MP
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# The final build step.
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$(BUILD_DIR)/$(TARGET_EXEC): $(OBJS)
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$(CXX) $(OBJS) -o $@ $(LDFLAGS)
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# Build step for C source
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$(BUILD_DIR)/%.c.o: %.c
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mkdir -p $(dir $@)
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$(CC) $(DEPFLAGS) $(CFLAGS) -c $< -o $@
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# Build step for C++ source
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$(BUILD_DIR)/%.cpp.o: %.cpp
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mkdir -p $(dir $@)
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$(CXX) $(DEPFLAGS) $(CXXFLAGS) -c $< -o $@
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.PHONY: clean
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clean:
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rm -r $(BUILD_DIR)
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.PHONY: run
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run: $(BUILD_DIR)/$(TARGET_EXEC)
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$(BUILD_DIR)/$(TARGET_EXEC)
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# Include the .d makefiles. The - at the front suppresses the errors of missing
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# Makefiles. Initially, all the .d files will be missing, and we don't want those
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# errors to show up.
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-include $(DEPS)
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